1. Field of the Invention
This invention relates generally to improvements in digital audio processing, and relates specifically to a system and method for computing and encoding an error detection sequence in digital audio encoding.
2. Description of the Background Art
Digital audio is now in widespread use in digital video disk (DVD) players, digital satellite systems (DSS), and digital television (DTV). Each of these systems has incorporated digital audio compression in order to fit more digital audio in a storage device of limited storage capacity, or to transmit digital audio over a channel of limited bandwidth. As part of the digital audio compression method used, steps must be taken to ensure against errors in the transmission of the data. The transmission may take many forms, including encoding and writing data to a disk and subsequently reading and decoding data from it, or direct radio-frequency broadcast from a encoder and transmitter to a receiver and decoder. In most cases, additional bits may be added by the transmitter (and encoder) to the digital audio data so that the receiver (and decoder) can evaluate the received data for the presence or absence of errors.
A frame check sequence (FCS) is a number which, when appended to a transmitted message, allows the receiver to deduce the presence or absence of errors in transmission. The cyclic redundancy check (CRC) method considers the individual frames of data in a serial bitstream between a transmitter and a receiver to be large binary numbers. The transmitter in the CRC method divides each number by a fixed constant, and then examines the remainders. In the most common practice, these remainders, one example of an FCS, are appended to the end (i.e. the part arriving last in time) of the numbers. These appended numbers are then transmitted to the receiver. The receiver then divides the appended numbers by the same fixed constant previously used by the transmitter. If the new remainders of these divisions are 0, then the receiver may deduce that it received the frames in the serial bitstream without errors.
Because binary division consists primarily of logical shifting of the data bits, a CRC FCS is commonly generated and evaluated using some form of hardware shift-register employing feedback. An advantage of many CRC embodiments which append the FCS at the end of the bitstream is that the same circuit design may be used to both generate the FCS in the transmitter and evaluate the FCS in the receiver. The FCS is generated by shifting the bitstream through the shift-register. The number remaining within the shift-register after the last bit of the bitstream has been shifted into the shift-register is used as the FCS. When this FCS is appended to the end of the bitstream, an identical shift-register in the receiver may be used to evaluate the incoming appended bitstream. After shifting the entire appended bitstream through the receiver's shift-register, if there are no errors from transmission the shift-register should contain binary 0.
One example of a transmitter sending data to a receiver is the digital audio compression method first used by Dolby.RTM. Labs. The Advanced Television Systems Committee (ATSC) selected this Dolby.RTM. Labs design for use in the digital television (DTV) system (formerly known as high-definition television, or HDTV). This design is set forth in the Audio Compression version 3 (AC-3) specification, document number ATSC A/52 (here after "the AC-3 specification"), which is hereby incorporated by reference. The AC-3 specification has been subsequently selected for Region 1 (North American market) DVD's and selected DSS broadcasts.
The AC-3 specification presents a standard decoder design for digital audio, which allows all AC-3 encoded digital audio recordings to be reproduced by differing vendors' equipment. Certain parts of the encoder design must also be standard in order that the resulting encoded digital audio may be reproduced with the standard decoder design. However, many of the design details in areas, such as the calculation and encoding of one of two cyclic redundancy check (CRC) frame check sequences (FCS), may be left to the individual designer with the requirement that the design does not affect the ability of the resulting encoded digital audio to be reproduced with the standard decoder design.
It is less common to append a FCS at the beginning (i.e. the part arriving first in time), rather than at the end, of a bitstream. However, the AC-3 specification provides for both an appended-at-the-beginning FCS, called CRC1, as well as an appended-at-the-end FCS, called CRC2. Furthermore, the AC-3 specification requires that no matter how CRC1 is generated it must be capable of evaluation using the same shift-register in the decoder as CRC2. No system or method capable of generating CRC1 is disclosed in the AC-3 specification.
Therefore, techniques for generating an appended-at-the-beginning CRC1 which may be evaluated by a standard appended-at-the-end shift-register remains a significant consideration in digital audio operations.